Semiconductors are vital to modern life. From the way we communicate and travel, to the cities we inhabit; from our dishwashers, microwaves and TVs, to our smartphones, PCs, and tablets, the chips we take for granted drive the devices we have come to rely on. Their use has revolutionized how we live, work, and play, enabling us to understand, create, and share information faster and more easily. Today, we expect devices to become smaller and more powerful every year, without fully understanding how.
SEMICONDUCTOR DEVICE MANUFACTURING
The process of manufacturing semiconductor devices on a wafer can be divided into three distinct parts:
- Wafer manufacturing;
- Transistor formation (known as Front-end of the line (FEOL) processing);
- Interconnect formation (known as Back-end of the line (BEOL) processing).
We develop, manufacture and sell equipment, and provide services used by semiconductor device manufacturers, at each stage.
In the wafer manufacturing process, a large single crystal of very pure silicon is grown from molten silicon. The crystal is then sliced into a large number of thin slices, or wafers, of single crystalline silicon. These slices are polished to an atomic-level flatness before the next steps are executed. For advanced applications, some layers are deposited on the wafer for later use, by either epitaxy or diffusion/oxidation. Epitaxial wafers are even flatter and contain fewer defects at the surface than polished wafers.
FROM WAFER TO DEVICES
During FEOL and BEOL wafer processing, multiple thin films of either electrically insulating material, also called dielectrics, or conductive material are modified, grown, or deposited on a silicon wafer. This involves the following steps:
- First, several material processing cycles are used in the FEOL to build the basic transistor and other components such as capacitors and resistors;
- Second, several processing cycles are used in the BEOL to electrically connect the large number of transistors and components, and to build additional passive components such as capacitors, inductors, and resistors. Patterning of deposited layers with lithography and etching (described below) creates the transistors, passive components, and connecting wires, which together make up the integrated circuit. Each integrated circuit is a single chip or a die on the wafer.
A finished wafer may contain several dozen to several thousand individual dies. Wafer processing is performed either one wafer at a time in single wafer processing systems or many wafers at a time in batch processing systems. Multiple deposition, and patterning processes are performed on the same wafer to complete a device.
The number and precise order of the process steps varies depending upon the complexity and design of the integrated circuit.
The performance of the circuit is determined in part by the various electrical characteristics of the materials used in the layers of the circuit and the wafer. Simple circuits may have as few as ten layers, while complex circuits may have more than one hundred layers. The device manufacturing process is capital-intensive, requiring multiple units of several different production systems. Many different but complementary methods are used to modify, grow, or deposit materials on the wafers. The device manufacturing process on the wafer is complete when all of the layers have been deposited and patterned on the wafer.
The introduction of even trace levels of foreign particles or material can make a circuit, or even an entire wafer, unusable.
To reduce the level of foreign particles or material, wafer processing is performed in cleanrooms with ultra-low particle and contamination levels. The correct electrical functioning of the integrated circuits on each die is confirmed by probing. Non-functioning circuits are marked so they can later be discarded before money is spent on packaging the chip. The yield – or the percentage of known good die for a mature process – is usually well above 95%. For a process in development, the yield can be substantially smaller, and it is important to improve this as quickly as possible as it determines, to a large extent, the profitability of our customers.
FRONT-END AND BACK-END PROCESSING
There are two basic segments of chip manufacturing to complete a final packaged chip product. We refer to them as wafer processing, and assembly and packaging. We are an equipment supplier for the Front-end part: wafer processing.
During wafer processing – the start of the manufacturing line – manufacturers process wafers made of silicon, on which the electrical components are formed. During assembly and packaging – the Back-end of the manufacturing line – the wafers are divided up into individual chips and tested before being assembled and packaged.
1. FROM SAND TO PURE SILICON
It all starts with one simple, common substance – sand. The silicon found in sand is in the form of silicon dioxide. To make chips, manufacturers need pure silicon, which means the first step in the process is to separate the silicon from the oxygen molecules. The pure silicon needed to make silicon chips can have only one foreign atom for every billion silicon atoms. It must also be in monocrystalline form. The way atoms are organized in this form of silicon is essential to some of the later processes.
2. WAFER BLANKS
The silicon is then extracted, or pulled, from liquid silicon in the form of long cylindrical ingots at around 1,400 degrees centigrade.
3. WAFERS ARE CUT
Wafers are then cut from the ingots before being polished to produce a smooth surface. They are then sent to chip manufacturers for processing. The following steps in wafer processing are then repeated many times to create the finished wafer containing chips.
4. COATING A WAFER
The wafer is put into a high-temperature furnace and exposed to oxygen, forming a layer of silicon dioxide on the surface.
Then chemical vapor deposition (CVD) is used to add a layer or film of nitride.
5. CREATING MASKS
Once the circuit layout of the chips has been designed, glass plates or masks are created which help copy the design onto the surface of the wafer. Several masks are used in sequence to add more complexity to the chips.
6. ADDING A PATTERN
Now comes the time to begin creating the design on the surface of the wafer using the masks as a guide. Photolithography, a type of optical printing, is used. The wafer is first coated with photoresist, which changes when exposed to ultraviolet (UV) light.
The mask is placed above the wafer and precisely aligned with it. UV light shining above the mask reacts with the exposed parts of the photoresist, creating a pattern. The wafer is covered with a developing solution to develop these patterns, which are then etched, leaving the parts not exposed to UV light intact. The surface now contains 'trenches' that run across the surface.
A dielectric or insulating film is deposited in the trenches by one of a number of deposition technologies such as CVD or ALD or PEALD. Gates are formed between the trenches, creating parts of the many millions of transistors that may be created on a single chip. Gates can be switched to allow charge carriers, such as electrons, to flow or to prevent them from flowing. Contacts are formed by each gate to create a source and drain. Ion implantation is used to implant special elements into the wafer for the source and drain. The charge carrier enters a gate channel at the source contact and exits at the drain contact.
Once the basic chip components have been created, they need to be connected. The same processes of lithography, etching, and deposition, are used to form trenches filled with metal connections. These connections between components are created not just on one level, but on many. The finished wafer will contain up to several thousand individual chips in a space of 200mm to 300mm, and some chips can hold billions of transistors.
7. WAFERS SEPARATED INTO INDIVIDUAL CHIPS
Once wafer processing has been completed, the finished wafers are transported to another plant for cutting, assembly, and packaging. The individual wafers are cut into separate chips.
8. LEAD FRAMES
The chips are then placed in a lead frame, forming a protective housing.
9. TESTING PACKING
Each chip is then tested before being packaged to be sent for placement on circuit boards.